The present invention relates to computer network interfacing and switching, and more particularly, to an apparatus and method for cascading multiple multiport network switches to increase the number of ports in a network switching arrangement.
A multiport network switch in a packet switching network is coupled to stations on the network through its multiple ports. Data sent by one station on a network to one or more other stations on the network are sent through the network switch. The data is provided to the network switch over a shared access medium according to, for example, an Ethernet protocol. The network switch, which receives the data at one of its multiple ports, determines the destination of the data frame from the data frame header. The network switch then transmits the data from the appropriate port to which the destination network station is connected.
A single Ethernet network switch may have a number of 10/100 Mb/s ports, equaling, for example, 12 ports. The number of end stations connected to the single network switch is limited by the number of ports (i.e., port density) of the network switch. However, today""s users of networking devices demand flexibility and scalability without such constraints. To address this need, manufacturers have developed modular architectures that enable cascading of identical networking devices or network switch modules. By cascading these equipment (or components) in a loop, port density can be readily increased without redesign or development of costly interfaces.
Unfortunately, as the number of cascaded switches increases, so does the system latency (i.e., the aggregate processing delay of the switches). This system latency is attributable in part by the manner in which the switches store and retrieve the data frames in memory. One traditional memory architecture employs individual, local memories for each cascaded switch, as shown in FIG. 1. In this example, three multiport switches 12a, 12b, and 12c are cascaded together to permit the exchange of data frames received by any one of the switches and subsequent forwarding of the data frames out of a different multiport switch. These switches 12a, 12b, and 12c have a memory interface, e.g., 44a, 44b, and 44c, respectively. These memory interfaces 44a, 44b, and 44c enable switches 12a, 12b, and 12c to access their respective memories 601a, 601b, and 601c to write and read the data frames.
For purposes of explanation, it is assumed that a data frame is received a port (i.e., receive port) on switch 12a and that the data frame is destined for a node attached to a port on a different switch 12c. Switch 12a first stores the received data frame in memory 600a, and then determines whether to forward the received data frame out of its own port or send it to the next switch in sequence. Because the data frame is not destined to any port of switch 12a, the data frame is retrieved from memory 600a and sent to the next switch 12b via switch 12a""s cascade port (i.e., the port to which the neighboring switches is connected). Upon receiving the data frame, switch 12b stores the data frame in memory 600b. Next, switch 12b examines the data frame and determines that it should be forwarded to switch 12c. Switch 12b forwards the data frame to switch 12c by reading the stored received data frame from memory 600b and sending it out its cascade port. When the data frame arrives at switch 12c, switch 12c writes the data frame into its memory 600c, in similar fashion as the other switches 12a and 12b. At this point, however, switch 12c determines that the data frame should be forwarded out one of its ports, which is connected to the destination node. Accordingly, switch 12c reads the stored data frame and forwards it out the appropriate port. As evident by this example, the data frame, as it is transferred from switch to switch is stored and read numerous times into the memories of the respective switches. The series of write and read operations impose cost delay in the switching system.
Hence, the delay in the switching system may cause the switch to be unable to process data packets fast enough relative to the network traffic, creating congestion conditions. In other words, the switch is no longer a non-blocking switch.
To address this latency problem, one proposed solution is to employ a common memory among the various switches. FIG. 2 illustrates such a system in which switches 12a, 12b, and 12c shared memory 701 via memory interfaces 44a, 44b, and 44c, respectively. Under this approach, each of the interfaces 44a, 44b, and 44c are required to have a wider data bus to maintain the speed of read and write accesses as compared to the individual memory arrangement of FIG. 8. For example, the bus width of the memory interfaces 44a, 44b, and 44c may need to increase to 128 bits. The main drawback with this common memory implementation is that the increase in memory bandwidth also results in a proportionate increase in the number of pins of the switches. An increase in the number of pins disadvantageously require more area on the circuit board, resulting in greater package cost.
There is need for cascading a plurality of multiport switches to increase port density, while minimizing system latency. There is also a need to increase memory bandwidth of the cascaded switch arrangement without increasing the number of pin counts.
These and other needs are obtained by the present invention, where a plurality of switch modules transfer frame data of a corresponding received frame as data units. The memory interface enables the transfer of data units between the multiport switch modules and a shared memory system, increasing the overall bandwidth between the memory system and the multiport switch module by the simultaneous access of multiple memories for transfer of multiple data units for a respective packets.
One aspect of the present invention provides a switching system. The switching system includes a plurality of buffer memories, and a plurality of multiport switch modules. Each multiport switch module includes a memory interface configured for outputting a data unit of a corresponding data frame being received, to one of a corresponding one of the buffer memories and another one of the multiport switch modules. The multiport switch modules are configured for supplying a group of the data units to the plurality of buffer memories, simultaneously during said each memory access cycle according to a prescribed access protocol.
Since each of the multiport switch modules supply the data units of the corresponding receive data frame to the plurality of buffer memories, each buffer memory may store frame data for different multiport switch modules. Moreover, the transfer of the data units according to prescribed access protocol enables concurrent and simultaneous access of all the buffer memories, enabling a higher overall effective memory bandwidth between the multiport switch modules and the plurality of buffer memories. One exemplary embodiment of this aspect involves transfer of the data units between memory interfaces according to prescribed access protocol, enabling the switch module to fully optimize data transfer between the multiport switch modules and buffer memories. Another exemplary embodiment of this aspect uses a distributed memory interface, which receives the data units each of the multiport switch modules and stores the data units in the buffer memories according to the prescribed access protocol. Hence, the memory bandwidth is substantially increased without increasing the pin count of the switch modules.
Another aspect of the present invention provides a method of storing data frames received by respective network switch modules. The method comprises scheduling in each network switch module a transfer of a data unit of a corresponding data frame being received, to one of a corresponding buffer memory and another one of the network switch modules each memory access cycle, and simultaneously supplying by the network switch modules the data units to the plurality of buffer memories.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.